// ******************************************************************************
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  jpg_sub_ctrl_reg_offset_field.h
// Project line  :
// Department    :  K3
// Version       :  1.0
// Date          :  2013/5/31
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// History       :  2018/03/16 17:38:29 Create file
// ******************************************************************************

#ifndef __JPG_SUB_CTRL_REG_OFFSET_FIELD_H__
#define __JPG_SUB_CTRL_REG_OFFSET_FIELD_H__

#define jpg_sub_ctrl_JPGENC_CLKEN_LEN    1
#define jpg_sub_ctrl_JPGENC_CLKEN_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SOFT_RST_LEN    1
#define jpg_sub_ctrl_JPGENC_SOFT_RST_OFFSET 0

#define jpg_sub_ctrl_JPGENC_MEM_CTRL_LEN    32
#define jpg_sub_ctrl_JPGENC_MEM_CTRL_OFFSET 0

#define jpg_sub_ctrl_JPGENC_IRQ_FORCE_LEN    5
#define jpg_sub_ctrl_JPGENC_IRQ_FORCE_OFFSET 16
#define jpg_sub_ctrl_JPGENC_IRQ_CLR_LEN      5
#define jpg_sub_ctrl_JPGENC_IRQ_CLR_OFFSET   0

#define jpg_sub_ctrl_JPGENC_IRQ_MASK_LEN    5
#define jpg_sub_ctrl_JPGENC_IRQ_MASK_OFFSET 0

#define jpg_sub_ctrl_JPGENC_IRQ_STATE_RAW_LEN     5
#define jpg_sub_ctrl_JPGENC_IRQ_STATE_RAW_OFFSET  16
#define jpg_sub_ctrl_JPGENC_IRQ_STATE_MASK_LEN    5
#define jpg_sub_ctrl_JPGENC_IRQ_STATE_MASK_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_AWADDR_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_AWADDR_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_ARADDR_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_ARADDR_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_L_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_L_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_M_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_M_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_H_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_AWUSER_H_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_L_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_L_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_M_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_M_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_H_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_ARUSER_H_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_AWCACHE_LEN    4
#define jpg_sub_ctrl_JPGENC_SHIM_AWCACHE_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_ARCACHE_LEN    4
#define jpg_sub_ctrl_JPGENC_SHIM_ARCACHE_OFFSET 0

#define jpg_sub_ctrl_JPGENC_SHIM_CTRL_LEN    32
#define jpg_sub_ctrl_JPGENC_SHIM_CTRL_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_CLKEN_0_LEN    1
#define jpg_sub_ctrl_JPGDEC_CLKEN_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_CLKEN_1_LEN    1
#define jpg_sub_ctrl_JPGDEC_CLKEN_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SOFT_RST_0_LEN    1
#define jpg_sub_ctrl_JPGDEC_SOFT_RST_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SOFT_RST_1_LEN    1
#define jpg_sub_ctrl_JPGDEC_SOFT_RST_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_SP_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_SP_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_SP_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_SP_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_TP_0_LEN    16
#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_TP_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_TP_1_LEN    16
#define jpg_sub_ctrl_JPGDEC_MEM_CTRL_TP_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_IRQ_FORCE_0_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_FORCE_0_OFFSET 16
#define jpg_sub_ctrl_JPGDEC_IRQ_CLR_0_LEN      4
#define jpg_sub_ctrl_JPGDEC_IRQ_CLR_0_OFFSET   0

#define jpg_sub_ctrl_JPGDEC_IRQ_FORCE_1_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_FORCE_1_OFFSET 16
#define jpg_sub_ctrl_JPGDEC_IRQ_CLR_1_LEN      4
#define jpg_sub_ctrl_JPGDEC_IRQ_CLR_1_OFFSET   0

#define jpg_sub_ctrl_JPGDEC_IRQ_MASK_0_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_MASK_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_IRQ_MASK_1_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_MASK_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_RAW_0_LEN     4
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_RAW_0_OFFSET  16
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_MASK_0_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_MASK_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_RAW_1_LEN     4
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_RAW_1_OFFSET  16
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_MASK_1_LEN    4
#define jpg_sub_ctrl_JPGDEC_IRQ_STATE_MASK_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWADDR_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWADDR_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWADDR_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWADDR_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARADDR_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARADDR_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARADDR_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARADDR_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_L_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_L_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_L_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_L_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_M_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_M_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_M_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_M_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_H_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_H_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_H_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_AWUSER_H_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_L_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_L_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_L_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_L_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_M_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_M_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_M_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_M_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_H_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_H_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_H_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_ARUSER_H_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWCACHE_0_LEN    4
#define jpg_sub_ctrl_JPGDEC_SHIM_AWCACHE_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_AWCACHE_1_LEN    4
#define jpg_sub_ctrl_JPGDEC_SHIM_AWCACHE_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARCACHE_0_LEN    4
#define jpg_sub_ctrl_JPGDEC_SHIM_ARCACHE_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_ARCACHE_1_LEN    4
#define jpg_sub_ctrl_JPGDEC_SHIM_ARCACHE_1_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_CTRL_0_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_CTRL_0_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_SHIM_CTRL_1_LEN    32
#define jpg_sub_ctrl_JPGDEC_SHIM_CTRL_1_OFFSET 0

#define jpg_sub_ctrl_CONTROL_DISABLE_AXI_DATA_PACKING_LEN    1
#define jpg_sub_ctrl_CONTROL_DISABLE_AXI_DATA_PACKING_OFFSET 16
#define jpg_sub_ctrl_JPG_TOP_APB_FORCE_CLK_ON_LEN            1
#define jpg_sub_ctrl_JPG_TOP_APB_FORCE_CLK_ON_OFFSET         3
#define jpg_sub_ctrl_JPG_DMA_FORCE_CLK_ON_LEN                1
#define jpg_sub_ctrl_JPG_DMA_FORCE_CLK_ON_OFFSET             2

#define jpg_sub_ctrl_CVDR_MEM_CTRL_LEN    32
#define jpg_sub_ctrl_CVDR_MEM_CTRL_OFFSET 0

#define jpg_sub_ctrl_CVDR_IRQ_FORCE_LEN    5
#define jpg_sub_ctrl_CVDR_IRQ_FORCE_OFFSET 16
#define jpg_sub_ctrl_CVDR_IRQ_CLR_LEN      5
#define jpg_sub_ctrl_CVDR_IRQ_CLR_OFFSET   0

#define jpg_sub_ctrl_CVDR_IRQ_MASK_LEN    5
#define jpg_sub_ctrl_CVDR_IRQ_MASK_OFFSET 0

#define jpg_sub_ctrl_CVDR_IRQ_STATE_RAW_LEN     5
#define jpg_sub_ctrl_CVDR_IRQ_STATE_RAW_OFFSET  16
#define jpg_sub_ctrl_CVDR_IRQ_STATE_MASK_LEN    5
#define jpg_sub_ctrl_CVDR_IRQ_STATE_MASK_OFFSET 0

#define jpg_sub_ctrl_CVDR_SOFT_RST_LEN    1
#define jpg_sub_ctrl_CVDR_SOFT_RST_OFFSET 0

#define jpg_sub_ctrl_JPG_CVDR_BUSY_LEN      1
#define jpg_sub_ctrl_JPG_CVDR_BUSY_OFFSET   5
#define jpg_sub_ctrl_JPG_JPGDEC_BUSY_LEN    4
#define jpg_sub_ctrl_JPG_JPGDEC_BUSY_OFFSET 1
#define jpg_sub_ctrl_JPG_JPGENC_BUSY_LEN    1
#define jpg_sub_ctrl_JPG_JPGENC_BUSY_OFFSET 0

#define jpg_sub_ctrl_DEBUG_INFO_0_LEN    32
#define jpg_sub_ctrl_DEBUG_INFO_0_OFFSET 0

#define jpg_sub_ctrl_DEBUG_INFO_1_LEN    32
#define jpg_sub_ctrl_DEBUG_INFO_1_OFFSET 0

#define jpg_sub_ctrl_DEBUG_INFO_2_LEN    32
#define jpg_sub_ctrl_DEBUG_INFO_2_OFFSET 0

#define jpg_sub_ctrl_DEBUG_INFO_3_LEN    32
#define jpg_sub_ctrl_DEBUG_INFO_3_OFFSET 0

#define jpg_sub_ctrl_JPGDEC_TZ_SECURE_N_LEN    4
#define jpg_sub_ctrl_JPGDEC_TZ_SECURE_N_OFFSET 2
#define jpg_sub_ctrl_JPGENC_TZ_SECURE_N_LEN    1
#define jpg_sub_ctrl_JPGENC_TZ_SECURE_N_OFFSET 1
#define jpg_sub_ctrl_TOP_TZ_SECURE_N_LEN       1
#define jpg_sub_ctrl_TOP_TZ_SECURE_N_OFFSET    0

#endif // __JPG_SUB_CTRL_REG_OFFSET_FIELD_H__
